Verilog Lab EE

Final is coming and I have no time to do this lab so ask somebody help me out.

This lab is successor of last lab, after u finish viewing the document attached and are sure can finish on time i will send u the code of last lab so that u can finish this lab. It is not hard just a weekly lab but u need to be proficient in writing ASSEMBLY code and Verilog. 

Please please view the document attached first and make sure u can do that before contacting me